1. Field of the Invention
This invention relates generally to systems for transferring synchronous digital signals across asynchronous boundaries and specifically to a clock synchronizer for transferring digital data at hardware-limited speeds between synchronous clock boundaries.
2. Discussion of the Related Art
In systems using digital circuitry, two functional blocks operating in two different timing domains often must communicate with one another. When these two blocks operate in synchrony with a single digital clock signal, transfer of digital data between the two is not a problem. However, when any two digital subsystems operate in synchrony with different clock signals, any digital data signals traveling between them must be synchronized in some manner to avoid hardware-related data errors.
If, for example, two digital subsystems operate in synchrony with different clocks (an external clock domain and an internal clock domain), digital data signals traveling from the external clock domain to the internal clock domain must be resynchronized with the internal clock signal. Similarly, signals traveling from the internal domain to the external domain must be resynchronized with the external clock signal at the asynchronous boundary. Without such resynchronization, hardware "metastability" problems produce invalid logic results in the receiving domain, as is well-known in the art. In a bistable latch where the coincident occurrence of two pulses (a data pulse and a clock pulse, for instance) is required to change the state of the latch, a "metastable" state may occur when the two actuating pulses do not overlap sufficiently in time to permit the bistable latch to completely switch from one stable state to the other. With insufficient overlap, such as can occur when the clock signal is poorly synchronized with the data pulse, the bistable latch output may appear to change states to the other stable level but may indeed move transiently from one level to the other and then back again. When actuated by signals from two different clock domains, the metastable latch problem occurs when the clock pulse from one domain overlaps insufficiently with the data pulse synchronized to the clock from the other domain. It is particularly difficult to correct for metastability occurring during synchronous data transfer across asynchronous boundaries because the two synchronous domain clocks continually drift in relative phase.
The well-known solution to the metastable latch problem is to hold the data pulse at the bistable latch for at least two clock intervals, thereby ensuring that the latch changes state during a second full overlapping clock pulse when the first partial overlapping clock pulse is insufficient to change the latch state. This is known in the art as "double-sampling" of the incoming data pulses at the asynchronous boundary. Disadvantageously, when two independent clock domains are operating at hardware-limited clock rates, it may not be possible for the hardware to support double-sampling of incoming data pulses because of speed limitations. For appreciation of metastable operation, reference is made to Marino ("General Theory of Metastable Operation" IEEE Trans. Computers, Vol. C-30, No. 2, pp. 107-115, Feb. 1981), for instance.
The digital systems art is replete with schemes for digital synchronization across asynchronous boundaries. For instance, several practitioners attack the metastability problem directly. In U.S. Pat. No. 5,132,990, Dukes proposes a high-speed data synchronizer that stores the synchronized data in a transparent latch instead of a flip-flop to avoid the long set-up times required by such devices and inserts a Schmitt trigger ahead of the transparent latch to function as a matched filter to eliminate runt pulses that may cause metastability problems. In U.S. Pat. No. 4,405,898, Flemming uses a pseudo-synchronous clocking scheme to synchronize two systems of synchronous logic with dissimilar maximum clocking rate requirements by using a single oscillating source to derive two different clock signals having mutual properties specifically designed to avoid metastability.
Some practitioners prefer master clock schemes for synchronizing different independent subsystem clocks. For instance, in U.S. Pat. No. 5,133,064, Hotta et al. proposes using an original clock oscillator to deliver a single clock signal to each digital subsystem wherein the "original" clock signal is employed to phase lock the local clock signals internal to each domain. In U.S. Pat. No. 4,569,065, Cukier discloses a phase-locked clock circuit with a special adjustment command mode for controlling clock phase.
Other practitioners propose a variety of creative solutions to related problems. For instance, in U.S. Pat. No. 5,291,529, Crook et al. discloses an improved handshaking method for cross-domain data transfers that uses knowledge of the measured interboundary clock phase differences to speed the acknowledgement process without degrading metastability immunity. In U.S. Pat. No. 4,926,451, Yoshihara et al. discloses a more efficient reset switch for synchronizing an on-chip IC clock circuit intended to operate in the GHz frequency region. In U.S. Pat. No. 4,868,548, Gelvin discloses a video cursor signal synchronizer that uses a random-access memory (RAM) addressing scheme to insert a video cursor into the raster at any sub-multiple of the video clock rate. In U.S. Pat. No. 4,843,263, Ando discloses a clock timing controller for a plurality of microchips that allows an individual chip to be disabled responsive to a gate triggered by the detection of unacceptable phase slippage in the individual chip clock.
Yet other practitioners suggest using delay lines to synchronize clock domains. For instance, in U.S. Pat. No. 5,295,164, Yamimura discloses a clock synchronizer that uses dual delay lines to minimize the actual delay needed to synchronize clock signals by operating near zero differential delay instead of operating near one clock interval of differential delay. In U.S. Pat. No. 5,305,354, Thaller et al. discloses a latency-reduction scheme for delay line synchronizers that uses an "abort" gate to discard invalid asynchronous inputs before they exit from the delay line. None of these various solutions is particularly workable for improving data transfer efficiency between domains in hardware speed-limited applications.
Clock multiplication and digital delay techniques appear to offer the best chance for avoiding the metastability problem during high-speed asynchronous data transfers. For instance, in U.S. Pat. No. 5,150,386, Stem et al. disclose a clock multiplier and jitter attenuator circuit that provides a phase-locked stable clock frequency that is some multiple of the average external clock frequency. Stem et al. propose loading incoming data from the external clock domain into a FIFO line of storage cells at the external clock rate and then reading out the FIFO storage line at an internal clock rate obtained by dividing the high-speed stable clock signal. The instantaneous jitter in the digital data stream is absorbed by the FIFO line. Stern et al. neither consider nor suggest how their technique could be applied to speed-limited asynchronous transfers in applications that cannot support a multiple clock frequency. Similarly, in U.S. Pat. No. 4,873,703, Crandall et al. disclose a brute-force synchronizing system that transfers data bytes at one clock rate to a data sink, which removes them at another clock rate. Their data sink is a RAM with the address logic required for independent read and write access. Although the Crandall et al. method successfully transfers data across an asynchronous boundary, they neither consider nor suggest synchronizing techniques suitable for hardware-limited transfer speeds that cannot support random access memory control overhead.
Perhaps the most promising class of solutions to the speed-limited asynchronous boundary metastability problem is the clock-division scheme proposed by several practitioners. For instance, in U.S. Pat. No. 4,975,702, Bazes discloses a CMOS waveform digitizer that uses two L-type registers to sample two versions of the analog input signals in parallel and in synchrony with the same clock signal to improve digital resolution without risking metastable latch states. In U.S. Pat. No. 5,034,967, Cox et al. discloses a digital synchronizer that produces a plurality of phase-shifted reference clock signals. Upon receiving an asynchronous event signal, the boundary-transfer logic examines these phase-shifted clock signal versions and selects one of them with which to sample the incoming asynchronous event signal, thereby avoiding metastable latch operation. In U.S. Pat. No. 5,256,912, Rios discloses a synchronizer apparatus wherein a plurality of clocking signals are generated by a specialized clocking circuit within a boundary synchronizer module incorporating transparent latches. Rios creates several master clock phase signals in each of many parallel synchronizer cells (one cell transfers one bit) and delays transfer of the data bit from each cell for at least one full master clock interval to permit settling and avoid metastability. Reference is also made Fuhs et al. ("Passing Data Stream Across Asynchronous Clock Domains in Scalable Coherent Interface Bus", IBM Technical Disclosure Bulletin, Vol. 36, No. 11, pp. 373-375, Nov. 1993) for a description of a method for passing a string of an unknown number of data words from one clock domain to another within a VLSI chip. Fuhs et al. propose using a storage array as a buffer between the two clock domains and disclose special logic necessary to control the reading from the array of the data words in the new clock domain. This logic uses a Sliding Window Synchronizer that polls a plurality of synchronizing latches to ensure that the incoming data words remain in the array for more than one clock interval to avoid metastability. Fuhs et al. neither consider nor suggest how their high-speed window polling scheme can be applied to synchronize data transfers at hardware-limited clocking speeds.
Accordingly, there is yet a clearly-felt need in the art for an asynchronous data transfer clock synchronizing scheme that avoids metastability when operating at the hardware speed limit that precludes analysis, measurement and frequency-multiplication. The related unresolved problems and deficiencies are clearly felt in the art and are solved by this invention in the manner described below.